Eecient Use of Processing Transistors for Larger On-chip Storage: Multithreading 1

The current trend of aggressive dynamic scheduling in superscalar processors is reaching a point of diminishing returns. This calls for an architecture that utilizes the processing transistors better, thereby freeing up space to be used for more on-chip storage. Recent proposals have included multiple conventional superscalars on a chip (which we call superchip) and multithreaded superscalars, also called simultaneous multithreaded (SMT) processors. In the past, these systems have been compared in the context of sequential applications. In this paper, we focus on a wide range of parallel applications. We show that, in low-end machines with only one processor chip on which to run the multiple threads, in-order issue SMTs achieve a performance that is more stable and, on average, higher than out-of-order issue superchips. In high-end machines with several processor chips working on the same application, however, the higher demands on the processors often make out-of-order issue a requirement. While a fully dynamic SMT design is too expensive, a very cost-eeective organization is several low-issue dynamic SMT processors sharing a chip. Overall, SMTs deliver high performance because they adapt to the speciic thread-and instruction-level parallelism of the application. They utilize the processing transistors more effectively , thereby freeing up space to be used for more on-chip storage.